Updated docs

diff --git a/electronics/Makefile b/electronics/Makefile
index be5c47b2ffb8e1595340c8ee1eb9979c85905c73..337ae12dcd737371bed977b85bd77c4035db2288 100644 (file)
--- a/electronics/Makefile
+++ b/electronics/Makefile
@@ -35,4 +35,4 @@ tidy:
          *.bak *.log *.backup
 
 clean: tidy
-       rm -f *.cnc *.gbr $(NAME).zip $(NAME).net
+       rm -f *.cnc *.gbr $(NAME).zip $(NAME).net $(NAME).bom

diff --git a/electronics/README.md b/electronics/README.md
index 7ec3abaefa6a00e2ceedf0e1fac583ac0720a372..1fcbac26e2dc82e902e16756c49ba10f12338b97 100644 (file)
--- a/electronics/README.md
+++ b/electronics/README.md
@@ -8,19 +8,26 @@ You must have ``make`` and the GEDA tools install.  Other make commands are:
 
   * ``pcb`` - Open the PCB editor.
   * ``bom`` - Create a Bill of Materials file in ``buildbotics_controller.bom``.
-  * ``allegro`` - Craete an Allegro netlist file.
+  * ``net`` - Generate the netlist as ``buildbotics_controller.net``.
+  * ``drc`` - Run the Design Rule Checker.
   * ``layout`` - Initialize the PCB layout.
   * ``attrib`` - Edit schematic part attributes.
   * ``zip`` - Create a zip file from the Gerber and drill files.
+  * ``tidy`` - Remove all backup files.
   * ``clean`` - Remove all autogenerated files.
 
 # Configuration notes
-Copy the ``system-gnetlistrc`` file to ``~/.gEDA/gnetlistrc``, comment out
-(insert semi;colon) the line that reads:
+Copy the system gnetlistrc file:
+
+    mkdir -p ~/.gEDA
+    /etc/gEDA/system-gnetlistrc ~/.gEDA/gnetlistrc
+
+Edit ``~/.gEDA/gnetlistrc`` and comment out (insert semicolon) the line that
+reads:
 
     (hierarchy-netattrib-mangle "enabled")
 
-and uncomment remove semi-colon the line that reads
+and uncomment the line that reads:
 
     ;(hierarchy-netattrib-mangle "disabled")
 
@@ -30,7 +37,9 @@ The resulting lines should look like this:
     (hierarchy-netattrib-mangle "disabled")
 
 This allows power and ground rails to be routed between schematics without
-mangling the names.
+mangling the names.  Note, that as a consequence of this setting you cannot
+use ``net`` or ``netname`` attributes in any schematic modules that are used
+more than once with out having them all connected together.
 
 Set the library path in PCB to point to the local footprints folder.  Use
 ``File->Preferences->Library`` in PCB to do this.