From: Joseph Coffland <joseph@cauldrondevelopment.com>
Date: Wed, 19 Oct 2016 09:52:17 +0000 (-0700)
Subject: Improved power conditioning simulation
X-Git-Url: https://git.buildbotics.com/?a=commitdiff_plain;h=02c15efb7eee5cab76e9cfb0ca5387c725c426f0;p=bbctrl-pcb

Improved power conditioning simulation
---

diff --git a/spice/.gitignore b/spice/.gitignore
new file mode 100644
index 0000000..94f21b3
--- /dev/null
+++ b/spice/.gitignore
@@ -0,0 +1,3 @@
+*.net
+*.log
+*.raw
diff --git a/spice/power_cond.asc b/spice/power_cond.asc
index 14d4781..5882ae1 100644
--- a/spice/power_cond.asc
+++ b/spice/power_cond.asc
@@ -1,162 +1,144 @@
 Version 4
 SHEET 1 2268 1624
-WIRE -864 -160 -976 -160
-WIRE -672 -160 -768 -160
-WIRE -240 -160 -672 -160
-WIRE 128 -160 -240 -160
-WIRE 320 -160 128 -160
-WIRE 512 -160 320 -160
-WIRE -240 -112 -240 -160
-WIRE 320 -112 320 -160
-WIRE -672 -80 -672 -160
-WIRE 128 0 128 -160
-WIRE -784 16 -784 -112
-WIRE -672 16 -672 -16
-WIRE -672 16 -784 16
-WIRE -240 16 -240 -32
-WIRE -192 16 -240 16
-WIRE 80 16 -112 16
-WIRE 512 16 512 -160
-WIRE 208 32 192 32
-WIRE 320 32 320 -32
-WIRE 320 32 288 32
-WIRE 368 32 320 32
-WIRE 464 32 368 32
-WIRE -976 48 -976 -160
-WIRE 80 48 -16 48
-WIRE -480 96 -560 96
-WIRE -400 96 -432 96
-WIRE -352 96 -400 96
-WIRE -240 96 -240 16
-WIRE -240 96 -272 96
-WIRE -16 96 -16 48
-WIRE -16 96 -160 96
-WIRE -480 112 -480 96
-WIRE -784 128 -784 16
-WIRE -240 144 -240 96
-WIRE -160 144 -160 96
-WIRE -16 160 -16 96
-WIRE 16 160 -16 160
-WIRE 512 160 512 112
-WIRE 512 160 96 160
-WIRE 608 160 512 160
-WIRE 736 160 608 160
-WIRE -16 176 -16 160
-WIRE 736 176 736 160
-WIRE -560 192 -560 176
-WIRE -480 192 -480 160
-WIRE -480 192 -560 192
-WIRE 608 192 608 160
-WIRE -976 288 -976 128
-WIRE -784 288 -784 208
-WIRE -784 288 -976 288
-WIRE -560 288 -560 192
-WIRE -560 288 -784 288
-WIRE -432 288 -432 176
-WIRE -432 288 -560 288
-WIRE -240 288 -240 208
-WIRE -240 288 -432 288
-WIRE -160 288 -160 208
-WIRE -160 288 -240 288
-WIRE -16 288 -16 256
-WIRE -16 288 -160 288
-WIRE 128 288 128 64
-WIRE 128 288 -16 288
-WIRE 608 288 608 256
-WIRE 608 288 128 288
-WIRE 736 288 736 256
-WIRE 736 288 608 288
-WIRE -976 320 -976 288
-FLAG -976 320 0
-FLAG 736 160 Vs
-FLAG 368 32 gate
-FLAG -400 96 sw
-SYMBOL voltage -976 32 R0
+WIRE -816 -48 -848 -48
+WIRE -672 -48 -720 -48
+WIRE -528 -48 -672 -48
+WIRE -368 -48 -528 -48
+WIRE -160 -48 -368 -48
+WIRE -48 -48 -160 -48
+WIRE -672 -16 -672 -48
+WIRE -528 -16 -528 -48
+WIRE -160 -16 -160 -48
+WIRE -736 64 -736 0
+WIRE -672 64 -672 48
+WIRE -672 64 -736 64
+WIRE -368 96 -368 -48
+WIRE -848 112 -848 -48
+WIRE -624 112 -672 112
+WIRE -528 112 -528 64
+WIRE -528 112 -576 112
+WIRE -416 112 -528 112
+WIRE -48 112 -48 -48
+WIRE -624 128 -624 112
+WIRE -272 128 -304 128
+WIRE -160 128 -160 64
+WIRE -160 128 -192 128
+WIRE -112 128 -160 128
+WIRE -96 128 -112 128
+WIRE -416 144 -448 144
+WIRE -368 176 -368 160
+WIRE -672 208 -672 192
+WIRE -624 208 -624 176
+WIRE -624 208 -672 208
+WIRE -576 208 -576 192
+WIRE -576 208 -624 208
+WIRE -448 208 -448 144
+WIRE -736 224 -736 64
+WIRE -624 224 -624 208
+WIRE -528 224 -528 112
+WIRE -448 256 -448 208
+WIRE -400 256 -448 256
+WIRE -160 256 -320 256
+WIRE -48 256 -48 208
+WIRE -48 256 -160 256
+WIRE -160 272 -160 256
+WIRE -528 288 -528 224
+WIRE -448 288 -448 256
+WIRE -48 288 -48 256
+WIRE -848 384 -848 192
+WIRE -736 384 -736 304
+WIRE -736 384 -848 384
+WIRE -528 384 -528 352
+WIRE -528 384 -736 384
+WIRE -448 384 -448 368
+WIRE -448 384 -528 384
+WIRE -160 384 -160 352
+WIRE -160 384 -448 384
+WIRE -48 384 -48 352
+WIRE -48 384 -160 384
+WIRE -848 400 -848 384
+FLAG -848 400 0
+FLAG -160 256 Vs
+FLAG -112 128 gate
+FLAG -528 224 ref
+FLAG -368 176 0
+FLAG -448 208 comp
+FLAG -624 224 0
+SYMBOL voltage -848 96 R0
 WINDOW 3 40 45 Left 2
 WINDOW 123 0 0 Left 2
-WINDOW 39 35 80 Left 2
 SYMATTR Value 28
 SYMATTR SpiceLine Rser=.02
 SYMATTR InstName V1
-SYMBOL res -800 112 R0
+SYMBOL res -752 208 R0
 SYMATTR InstName R1
 SYMATTR Value 1k
 SYMATTR SpiceLine tol=1 pwr=.125
-SYMBOL polcap 592 192 R0
+SYMBOL polcap -64 288 R0
 WINDOW 3 24 56 Left 2
 SYMATTR Value 7800µ
 SYMATTR InstName CL
 SYMATTR SpiceLine V=35 Irms=3.67 Rser=0.03 Lser=0
 SYMATTR Description Capacitor
 SYMATTR Type cap
-SYMBOL res 720 160 R0
+SYMBOL res -176 256 R0
 SYMATTR InstName RL
 SYMATTR Value 24
-SYMBOL zener -656 -16 R180
+SYMBOL zener -656 48 R180
 WINDOW 0 24 64 Left 2
-WINDOW 3 -126 -1 Left 2
+WINDOW 3 6 67 Right 2
 SYMATTR InstName D1
 SYMATTR Value BZX84C12L
-SYMBOL pmos -864 -112 R270
-WINDOW 0 85 -13 VRight 2
-WINDOW 3 87 60 VRight 2
+SYMBOL pmos -816 0 R270
+WINDOW 0 -14 29 VRight 2
+WINDOW 3 69 -28 VRight 2
 SYMATTR InstName U1
 SYMATTR Value IPD90P04P4L-04_L0
 SYMATTR Prefix X
-SYMBOL pmos 464 112 M180
-WINDOW 3 66 63 Left 2
+SYMBOL pmos -96 208 M180
+WINDOW 3 68 178 VLeft 2
+WINDOW 0 -28 46 Left 2
 SYMATTR Value IPD90P04P4L-04_L0
 SYMATTR InstName U3
 SYMATTR Prefix X
-SYMBOL cap -256 144 R0
+SYMBOL cap -544 288 R0
 SYMATTR InstName C1
-SYMATTR Value 2.2µ
-SYMBOL res -256 -128 R0
+SYMATTR Value 1µ
+SYMBOL res -544 -32 R0
 SYMATTR InstName R2
-SYMATTR Value 200k
-SYMBOL res 112 144 R90
-WINDOW 0 0 56 VBottom 2
-WINDOW 3 32 56 VTop 2
-SYMATTR InstName R3
-SYMATTR Value 10k
-SYMBOL res 0 272 R180
-WINDOW 0 36 76 Left 2
-WINDOW 3 36 40 Left 2
-SYMATTR InstName R4
-SYMATTR Value 10k
-SYMBOL res -96 0 R90
-WINDOW 0 0 56 VBottom 2
-WINDOW 3 32 56 VTop 2
-SYMATTR InstName R5
-SYMATTR Value 1m
-SYMBOL res 304 -128 R0
+SYMATTR Value 1meg
+SYMBOL res -176 -32 R0
 SYMATTR InstName R6
 SYMATTR Value 20k
-SYMBOL res 304 16 R90
+SYMBOL res -176 112 R90
 WINDOW 0 0 56 VBottom 2
 WINDOW 3 32 56 VTop 2
 SYMATTR InstName R7
-SYMATTR Value 100k
-SYMBOL cap -176 144 R0
-SYMATTR InstName C2
-SYMATTR Value 2.2n
-SYMBOL LM293 128 48 R0
+SYMATTR Value 49k9
+SYMBOL LM293 -368 144 R0
+WINDOW 0 38 33 Bottom 2
+WINDOW 3 45 -71 Top 2
 SYMATTR InstName U2
-SYMBOL sw -432 192 M180
-WINDOW 3 -36 126 Left 2
-SYMATTR InstName S1
+SYMBOL sw -576 208 M180
+WINDOW 3 42 57 Invisible 2
+WINDOW 0 -12 113 Left 2
 SYMATTR Value OURSW
-SYMBOL voltage -560 80 R0
-WINDOW 3 -63 138 Left 2
+SYMATTR InstName S1
+SYMBOL voltage -672 96 R0
+WINDOW 3 -61 -8 Invisible 2
 WINDOW 123 0 0 Left 2
 WINDOW 39 0 0 Left 2
+WINDOW 0 -18 1 Left 2
+SYMATTR Value PULSE(0 5 0 10n 10n .5 1 4)
 SYMATTR InstName V2
-SYMATTR Value PULSE(0 5 0 0 0 .5 1 4)
-SYMBOL res -256 80 R90
+SYMBOL res -304 240 R90
 WINDOW 0 0 56 VBottom 2
 WINDOW 3 32 56 VTop 2
-SYMATTR InstName R8
-SYMATTR Value 100
-TEXT -1056 408 Left 2 !.tran 0 2.5 0 startup
+SYMATTR InstName R3
+SYMATTR Value 20k
+SYMBOL res -464 272 R0
+SYMATTR InstName R4
+SYMATTR Value 5k9
+TEXT -1056 408 Left 2 !.tran 1.6 startup
 TEXT -1056 448 Left 2 !.lib OptiMOS-P2_40V.lib
 TEXT -1056 488 Left 2 !.model OURSW SW(ROn=.01 Roff=10Meg Vt=3 Vh=0)
diff --git a/spice/power_cond.plt b/spice/power_cond.plt
new file mode 100644
index 0000000..dc1eb84
--- /dev/null
+++ b/spice/power_cond.plt
@@ -0,0 +1,14 @@
+[Transient Analysis]
+{
+   Npanes: 1
+   {
+      traces: 6 {524294,2,"V(Vs)*Ix(U3:D)+V(gate)*Ix(U3:G)+V(N002)*Ix(U3:S)"} {268959746,0,"V(vs)"} {524291,0,"V(ref)"} {524292,0,"V(comp)"} {268959751,0,"V(gate)"} {34603013,1,"I(Cl)"}
+      X: (' ',1,0,0.2,1.6)
+      Y[0]: (' ',0,-6,3,33)
+      Y[1]: (' ',1,-1.5,0.3,1.5)
+      Volts: (' ',0,0,3,-6,3,33)
+      Amps: (' ',0,0,0,-1.5,0.3,1.5)
+      Units: "W" (' ',0,0,3,-3,3,33)
+      Log: 0 0 0
+   }
+}