Doug Coffland [Fri, 7 Aug 2020 13:59:54 +0000 (06:59 -0700)]
resized board back to 142.3 mm wide
Doug Coffland [Fri, 7 Aug 2020 06:16:16 +0000 (23:16 -0700)]
removed resistors and caps, and added diodes on 3.3V inputs, added 3.3V to 5V level shifters on outputs, replaced level shifters on LCD interface
Joseph Coffland [Wed, 29 Jul 2020 23:15:38 +0000 (16:15 -0700)]
Switched from GPL to CERN-OHL-S license
Joseph Coffland [Thu, 24 Oct 2019 22:14:39 +0000 (15:14 -0700)]
Realign with 0.25mm grid
Doug Coffland [Thu, 24 Oct 2019 20:37:21 +0000 (13:37 -0700)]
removed gerbers, except for gerbers.zip, changed outlines for PC/R31 and P/L1, FreeDFM passed on these changes
Doug Coffland [Thu, 24 Oct 2019 16:44:00 +0000 (09:44 -0700)]
increased hole size for PC/R31, reduced pad size for P/L1, changed board rev to R13,updated pcb with new footprints for PC/R31 and P/L1
Joseph Coffland [Sun, 29 Sep 2019 21:27:45 +0000 (14:27 -0700)]
Fixed two new DRC errors that showed up with PCB 4.2.0
Doug Coffland [Fri, 20 Sep 2019 02:58:06 +0000 (19:58 -0700)]
adjusted size of solder clearance on pads on P/u2 to pass freedfm, removed and added PC/R36 to get resistor value to take in the bom file
Joseph Coffland [Thu, 19 Sep 2019 22:34:04 +0000 (15:34 -0700)]
Removed unused files
Joseph Coffland [Thu, 19 Sep 2019 22:32:02 +0000 (15:32 -0700)]
PCB/schematic corrections
Doug Coffland [Thu, 19 Sep 2019 22:12:06 +0000 (15:12 -0700)]
added V12 to silkscreen and fiddled with R36 in Power conditioner schematic
Joseph Coffland [Fri, 13 Sep 2019 02:00:23 +0000 (19:00 -0700)]
Removed old test circuits
Joseph Coffland [Fri, 13 Sep 2019 01:35:58 +0000 (18:35 -0700)]
20k -> 49.9k
Joseph Coffland [Thu, 12 Sep 2019 21:34:23 +0000 (14:34 -0700)]
10k -> 20k
Joseph Coffland [Thu, 12 Sep 2019 21:16:57 +0000 (14:16 -0700)]
Updated copyright and version numbers, Force shunt on when controller is off
Joseph Coffland [Tue, 9 Oct 2018 03:04:27 +0000 (20:04 -0700)]
Added test point to extra AVR pin
Joseph Coffland [Wed, 5 Sep 2018 08:21:05 +0000 (01:21 -0700)]
Added more filtering on quad FET current outputs
Joseph Coffland [Fri, 31 Aug 2018 21:44:58 +0000 (14:44 -0700)]
Fixed min mask
Joseph Coffland [Fri, 31 Aug 2018 21:08:34 +0000 (14:08 -0700)]
Merge branch 'master' of github.com:buildbotics/bbctrl-pcb
Joseph Coffland [Fri, 31 Aug 2018 21:08:27 +0000 (14:08 -0700)]
Updated v11 pdfs
Doug Coffland [Mon, 27 Aug 2018 21:28:22 +0000 (14:28 -0700)]
fixed solder mask clearances aroun vias
Joseph Coffland [Sun, 26 Aug 2018 23:23:48 +0000 (16:23 -0700)]
Cleaned up PCB, moved 0-10v to D/J2
Doug Coffland [Sun, 26 Aug 2018 19:21:51 +0000 (12:21 -0700)]
marked d/j2 as (do not populate) in schematic
Doug Coffland [Sun, 26 Aug 2018 17:28:56 +0000 (10:28 -0700)]
moved (do not populate" text to documetation attribute for H/C1 to be compatible with my bom file generator
Doug Coffland [Sun, 26 Aug 2018 17:10:32 +0000 (10:10 -0700)]
depopulated H/U1
Doug Coffland [Sat, 25 Aug 2018 22:28:55 +0000 (15:28 -0700)]
moved surface lines 3mm from edge of the board
Doug Coffland [Thu, 23 Aug 2018 23:42:06 +0000 (16:42 -0700)]
moved caps on input lines on DB25 connector to the other side of the resistor
Joseph Coffland [Thu, 16 Aug 2018 09:23:28 +0000 (02:23 -0700)]
Added PCB PDF
Joseph Coffland [Thu, 16 Aug 2018 09:11:38 +0000 (02:11 -0700)]
Added 0-10v circuit, changed low-pass filter values, rearranged motor step/dir headers, removed 3.3v output resistor, Changed 3.3v regulator, 5Ohm shunt, added missing cap on analog2
Joseph Coffland [Wed, 8 Aug 2018 01:24:16 +0000 (18:24 -0700)]
Removed filter from spindle PWM output
Joseph Coffland [Wed, 8 Aug 2018 01:07:42 +0000 (18:07 -0700)]
v11 changes
Joseph Coffland [Wed, 8 Aug 2018 00:22:00 +0000 (17:22 -0700)]
Ignore .xlsx
Joseph Coffland [Wed, 8 Aug 2018 00:14:26 +0000 (17:14 -0700)]
Remove .fp in PCB footprint names
Joseph Coffland [Mon, 7 May 2018 20:05:19 +0000 (13:05 -0700)]
More space around P/C7
Joseph Coffland [Mon, 7 May 2018 19:57:27 +0000 (12:57 -0700)]
Removed .fp in footprint attributes
Joseph Coffland [Mon, 7 May 2018 19:49:05 +0000 (12:49 -0700)]
Resolved conflicts
Joseph Coffland [Mon, 7 May 2018 19:36:00 +0000 (12:36 -0700)]
Improved H/L1 footprint
Joseph Coffland [Mon, 7 May 2018 19:13:25 +0000 (12:13 -0700)]
Small adjustments
Doug Coffland [Sat, 24 Feb 2018 04:34:18 +0000 (20:34 -0800)]
replaced PC/D1, PC/D3, and PC/D5 with new diode and updated footprint
Joseph Coffland [Tue, 16 Jan 2018 01:41:59 +0000 (17:41 -0800)]
Swapped load switch nets 1<->2
Doug Coffland [Wed, 13 Dec 2017 04:55:38 +0000 (20:55 -0800)]
changed H/R25 from 26.1 to 27 ohms because Elecrow could not source the 26.1 on the last batch.
Doug Coffland [Wed, 13 Dec 2017 04:51:47 +0000 (20:51 -0800)]
added solder mask clearance on vias under pad for P/Z2 to make FreeDFM happy
Joseph Coffland [Sat, 9 Dec 2017 22:13:04 +0000 (14:13 -0800)]
Removed unused STL40DN3LLH5 from schematic
Joseph Coffland [Mon, 4 Dec 2017 19:34:29 +0000 (11:34 -0800)]
Moved power plan away from edge
Joseph Coffland [Mon, 4 Dec 2017 02:26:07 +0000 (18:26 -0800)]
Added missing file
Joseph Coffland [Mon, 4 Dec 2017 02:20:21 +0000 (18:20 -0800)]
version
Joseph Coffland [Mon, 4 Dec 2017 02:18:04 +0000 (18:18 -0800)]
Moved Vcc test-point, Moved vias and power trace away from edge, Removed Do not populate from R/R15, Swapped RX/TX, Changed PC/R20 to 37.4 Ohm, Marked direction of ISP headers
Joseph Coffland [Mon, 30 Oct 2017 03:44:06 +0000 (20:44 -0700)]
Fixed solder mask openings, silk overlaps, improved layout, moved Vs and Vcc test points.
Doug Coffland [Sun, 29 Oct 2017 01:32:47 +0000 (18:32 -0700)]
subtle schematic changes for cleaning up BOM
Doug Coffland [Sat, 28 Oct 2017 23:31:04 +0000 (16:31 -0700)]
V9 board layout complete, no DRC or DFM errors. added footprints for new fets for clamping ciruit, changed motor_driver and rpi_bus schematics to have individual zero ohm resistors for each motor driver 5V supply. Moved R15 behind C4 and C6 in power.sch. Assigned footprints in power_conditioner.sch
Doug Coffland [Thu, 26 Oct 2017 17:39:53 +0000 (10:39 -0700)]
locked all test jig test points in pcb
Joseph Coffland [Sat, 21 Oct 2017 10:34:30 +0000 (03:34 -0700)]
Fix rpi bus
Joseph Coffland [Sat, 21 Oct 2017 10:32:51 +0000 (03:32 -0700)]
Merge branch 'no-iso' of github.com:buildbotics/bbctrl-pcb into no-iso
Joseph Coffland [Sat, 21 Oct 2017 10:25:24 +0000 (03:25 -0700)]
Try powering DRV8711 logic, Replaced P/R2 with 1.37k 1% to make sure U2 turns at 12v, Finished removing iso, Added shunt circuit
Joseph Coffland [Tue, 3 Oct 2017 04:55:22 +0000 (21:55 -0700)]
Remove iso
Joseph Coffland [Sat, 21 Oct 2017 10:25:24 +0000 (03:25 -0700)]
Try powering DRV8711 logic, Replaced P/R2 with 1.37k 1% to make sure U2 turns at 12v, Finished removing iso, Added shunt circuit
Joseph Coffland [Tue, 3 Oct 2017 04:55:36 +0000 (21:55 -0700)]
Merge branch 'master' of github.com:buildbotics/bbctrl-pcb
Joseph Coffland [Tue, 3 Oct 2017 04:55:22 +0000 (21:55 -0700)]
Remove iso
Joseph Coffland [Tue, 3 Oct 2017 04:52:23 +0000 (21:52 -0700)]
Added pcb pdf
Doug Coffland [Mon, 2 Oct 2017 02:26:27 +0000 (19:26 -0700)]
created test board for clamper circuit
Doug Coffland [Thu, 28 Sep 2017 02:18:06 +0000 (19:18 -0700)]
Merge branch 'master' of github.com:buildbotics/bbctrl-pcb
Joseph Coffland [Fri, 1 Sep 2017 21:52:19 +0000 (14:52 -0700)]
Updated version and added PDF output. Closes #16
Joseph Coffland [Thu, 13 Jul 2017 23:44:46 +0000 (16:44 -0700)]
AVR 22pF -> 10pF caps, per AVR1003 app note
Joseph Coffland [Mon, 10 Jul 2017 23:26:23 +0000 (16:26 -0700)]
Fixed Pwr AVR power. Vdd -> v3.3m. Oops!
Doug Coffland [Sat, 1 Jul 2017 14:36:20 +0000 (07:36 -0700)]
corrected part number for R/U4
Joseph Coffland [Thu, 29 Jun 2017 23:44:33 +0000 (16:44 -0700)]
Removed SCL line resistor to enable slave clock stretching
Joseph Coffland [Thu, 29 Jun 2017 22:20:10 +0000 (15:20 -0700)]
Moved Vout pwr input to PA7 to avoid problem with PC2
Joseph Coffland [Thu, 29 Jun 2017 21:07:37 +0000 (14:07 -0700)]
Small silk fix
Joseph Coffland [Thu, 29 Jun 2017 21:07:25 +0000 (14:07 -0700)]
Use 1% resistors for voltage dividers
Joseph Coffland [Wed, 28 Jun 2017 07:05:35 +0000 (00:05 -0700)]
Fixed silk error
Joseph Coffland [Fri, 16 Jun 2017 20:15:36 +0000 (13:15 -0700)]
Layout tweaks. Fixed silk over vias
Doug Coffland [Fri, 16 Jun 2017 17:58:09 +0000 (10:58 -0700)]
Increased trace size on 3.3V line from RPI, Moved r/LV1/R1 slightly to the right to improve clearance, Moved vias and one component away from the edge of the board to avoid conflict with enclosure
Joseph Coffland [Thu, 15 Jun 2017 01:05:02 +0000 (18:05 -0700)]
Moved polys away from board edges
Joseph Coffland [Wed, 14 Jun 2017 23:32:57 +0000 (16:32 -0700)]
Increase transistor pad size
Joseph Coffland [Wed, 14 Jun 2017 23:18:13 +0000 (16:18 -0700)]
Moved LCD connector
Joseph Coffland [Wed, 14 Jun 2017 23:09:55 +0000 (16:09 -0700)]
Small layout improvements
Joseph Coffland [Wed, 14 Jun 2017 22:25:10 +0000 (15:25 -0700)]
Fixed layer colors, Removed outline layer, Routed new analog_2 signal, Added two new guide holes
Joseph Coffland [Wed, 14 Jun 2017 22:24:41 +0000 (15:24 -0700)]
Added analog_2
Doug Coffland [Mon, 5 Jun 2017 22:06:41 +0000 (15:06 -0700)]
made all 10,000 ohm resistors have same value of 10K
Doug Coffland [Mon, 5 Jun 2017 04:46:40 +0000 (21:46 -0700)]
made corrections to part names so the BOM files build correctly, replace P/D3 model from V15P45-M3/86S to STPS3L40UF. V15P45 not available and STPS3L40UF is what is used in the demo board for the L7986A. Created new DO221 footprint file for STOS3L40UF. Corrected model number for P/PC/R20 and P/PC/R27
Doug Coffland [Tue, 30 May 2017 03:09:27 +0000 (20:09 -0700)]
Changed power such that second fet on smart fet is enabled through enable switch and delayed turnon. When second fet comes on, power is applied to the attiny and the 5V iso and 3.3Vm power supplies. Also removed resistor on rpi_sda_1:1. Added 130pf cap on rpi_reset:1 to fix invalid reboots. Corrected C3 and C2 on motor drivers.
Doug Coffland [Thu, 23 Mar 2017 21:47:13 +0000 (14:47 -0700)]
version sent to Elecrow for quote
Joseph Coffland [Tue, 21 Mar 2017 09:23:01 +0000 (02:23 -0700)]
Added Do not populate to test components
Joseph Coffland [Tue, 21 Mar 2017 08:55:35 +0000 (01:55 -0700)]
PCB fixes, removed 3.3v linear regulator, buck to 3.3v directly, updated copyright, added zero ohm resistors to isolate subcircuts.
Doug Coffland [Sun, 19 Mar 2017 18:27:32 +0000 (11:27 -0700)]
corrected enable circuit in power.sch to ensure that ISO 5V is off when enable is off
Doug Coffland [Sun, 19 Mar 2017 17:34:45 +0000 (10:34 -0700)]
rev 8 of buildbotics_controller, includes intelligent fet
Doug Coffland [Sat, 18 Mar 2017 20:33:56 +0000 (13:33 -0700)]
no comment
Doug Coffland [Wed, 8 Mar 2017 16:52:50 +0000 (08:52 -0800)]
corrected PGND in power_conditioner.sch and updated layout
Doug Coffland [Tue, 7 Mar 2017 22:08:51 +0000 (14:08 -0800)]
created power_conditioner.sch (and a symbol) from power_coind.sch and incorporated the result into power.sch. Also, changed C2 to .22uF 100V from 0.1uF 50V in motor_driver.sch and added resistors into low side gate circuits in motor_driver.sch. Updated SOD523 and TO252 footprints so they would not geterate silk screen errors in the DFM check. Completed layout and it passed DRC and FreeDFM tests.
Doug Coffland [Fri, 3 Mar 2017 05:35:36 +0000 (21:35 -0800)]
added diodes on outputs and added reverse battery battery circuit in parallel with zero ohm resistor in power_cond
Joseph Coffland [Tue, 28 Feb 2017 07:06:27 +0000 (23:06 -0800)]
Fixed silk
Doug Coffland [Tue, 28 Feb 2017 06:20:51 +0000 (22:20 -0800)]
corrected footprint attribute for ISP and J3 in power_cond.sch, corrected footprint for ATiny, completed layout in power_cond.pcb
Joseph Coffland [Tue, 28 Feb 2017 00:38:23 +0000 (16:38 -0800)]
Remove unused footprints
Joseph Coffland [Tue, 28 Feb 2017 00:34:57 +0000 (16:34 -0800)]
Removed unused symbols
Joseph Coffland [Tue, 28 Feb 2017 00:34:21 +0000 (16:34 -0800)]
Power cond fixes & cleanup
Doug Coffland [Mon, 27 Feb 2017 19:05:54 +0000 (11:05 -0800)]
corrected footprint for ATiny, started power_cond.pcb layout, corrected symbol for ATiny, added decoupling cap on ATiny in power_cond.sch and reconnected pin21 to gnd.
Doug Coffland [Mon, 27 Feb 2017 17:26:23 +0000 (09:26 -0800)]
new version of power_cond using quad intelligent fet
Doug Coffland [Sun, 26 Feb 2017 21:21:07 +0000 (13:21 -0800)]
latest power_cond sicruit with self protecting fet, also includes load circuit switches for testing
Joseph Coffland [Thu, 23 Feb 2017 02:45:36 +0000 (18:45 -0800)]
Fix grid alignment, moved power_cond3 -> power_cond
Doug Coffland [Tue, 21 Feb 2017 17:55:40 +0000 (09:55 -0800)]
changed value of sense resistor in power_cond3.sch