From 4489f1baf1f63cc8f710b62c400e8346866ffb33 Mon Sep 17 00:00:00 2001
From: Joseph Coffland <joseph@cauldrondevelopment.com>
Date: Sun, 31 Jan 2021 00:02:00 -0800
Subject: [PATCH] Fixes for demo

---
 Makefile               |  1 +
 src/avr/src/hardware.c | 12 ------------
 2 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/Makefile b/Makefile
index 5140c18..7234a51 100644
--- a/Makefile
+++ b/Makefile
@@ -46,6 +46,7 @@ html: $(HTML)
 resources: $(RESOURCES)
 
 demo: html resources bbemu
+	ln -sf ../../../$(TARGET_DIR) src/py/bbctrl/http
 	./setup.py install
 	cp src/avr/emu/bbemu /usr/local/bin
 
diff --git a/src/avr/src/hardware.c b/src/avr/src/hardware.c
index 43bda52..f79dffa 100644
--- a/src/avr/src/hardware.c
+++ b/src/avr/src/hardware.c
@@ -56,17 +56,6 @@ static hw_t hw = {{0}};
 
 
 static void _init_clock()  {
-#if 0 // 32Mhz Int RC
-  OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm;  // Enable 32MHz & 32KHz osc
-  while (!(OSC.STATUS & OSC_RC32KRDY_bm));      // Wait for 32Khz oscillator
-  while (!(OSC.STATUS & OSC_RC32MRDY_bm));      // Wait for 32MHz oscillator
-
-  // Defaults to calibrate against internal 32Khz clock
-  DFLLRC32M.CTRL = DFLL_ENABLE_bm;              // Enable DFLL
-  CCP = CCP_IOREG_gc;                           // Disable register security
-  CLK.CTRL = CLK_SCLKSEL_RC32M_gc;              // Switch to 32MHz clock
-
-#else
   // 12-16 MHz crystal; 0.4-16 MHz XTAL w/ 16K CLK startup
   OSC.XOSCCTRL = OSC_FRQRANGE_12TO16_gc | OSC_XOSCSEL_XTAL_16KCLK_gc;
   OSC.CTRL = OSC_XOSCEN_bm;                // enable external crystal oscillator
@@ -78,7 +67,6 @@ static void _init_clock()  {
 
   CCP = CCP_IOREG_gc;
   CLK.CTRL = CLK_SCLKSEL_PLL_gc;           // switch to PLL clock
-#endif
 
   OSC.CTRL &= ~OSC_RC2MEN_bm;              // disable internal 2 MHz clock
 }
-- 
2.27.0